Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods for fabricating high performance finFET devices.
Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure.
FinFET designs use “fins” that may be formed on the surface of a semiconductor wafer using selective-etching processes. The fins may be used to form a raised channel between the gate and the source and drain of a transistor. The gate is then deposited such that it wraps around the fin to form a trigate structure. Since the channel is extremely thin, the gate would generally have a greater control over the carriers within. However, when the transistor is switched on, the shape of the channel may limit the current flow. Therefore, multiple fins may be used in parallel to provide greater current flow for increased drive strength.
FIG. 1 illustrates a stylized cross-sectional depiction of a state-of-the-art FinFET device. A FinFET device 100 illustrated in FIG. 1 comprises a plurality of “fins” 110. The semiconductor device may be positioned in a vertical orientation, creating one or more fins 110. The source and drain of the FinFET are placed horizontally along the fin. A high-k metal gate 120 wraps over the fin, covering it on three sides. The gate 120 defines the length of the FinFET device. The current flow occurs along an orthogonal crystal plane in a direction parallel to the plane of the semiconductor wafer. The electrically significant height of the fin (labeled H) is typically determined by the amount of oxide recess in the fin reveal step and hence is constant for all fins 110.
The thickness of the fin (labeled Tfi) determines the short channel behavior of the transistor device and is usually small in comparison with the height H of the fin 110. The pitch (labeled P) of the fins is determined by lithographic constraints and dictates the wafer area to implement the desired device width. A small value of the pitch P and a large value of the height H enable a better packing of the devices per square area resulting in a denser design, or more efficient use of silicon wafer area.
The scaling down of integrated circuits coupled with higher performance requirements for these circuits have prompted an increased interest in finFETs. As such, there is an increased desire to form finFET devices with higher fins. Generally, the higher the fins of a finFET device, the higher the performance of that device. Utilizing taller fins, an increase in drive current may be realized, providing for devices that can operate at faster speed.
One problem exhibited by finFET devices is an uneven distribution of current density, i.e., the so-called current crowding effect. Further, aligning contact formation properly onto source or drain fins of finFET devices can be difficult. As such, designers are turned to forming epitaxy (EPI) layers or formations on fins of finFET devices. However, forming a proper amount of EPI formations on tall fins can be problematic, as illustrated by FIGS. 2-5 below.
FIG. 2 illustrates a stylized, cross-sectional view of a typical set of fins of a finFET device. FIG. 3 illustrates a stylized, cross-sectional view of typical finFET device having EPI formations on its fins. Referring simultaneously to FIGS. 2 and 3, finFET device 200 may be formed using various known processes. A plurality of fins 230 are formed on a silicon layer 210. A silicon oxide layer 220 is formed over the silicon layer 210. The fins 230 have a 1st height of “a.” FIGS. 2 and 3 show a recess line 240 at the top of the fins 230 after a typical hard mask strip process (e.g., strip of silicon nitride).
As shown in FIG. 3, epitaxy (EPI) growth/formation may be performed to form EPI formations 310 on the fins 230. The EPI formations 310 narrowly avoid contacting each other, but are formed in a diamond shape up to the recess line 240. The recess process reduces the fin height to the recess line 240. However, as noted above, there is a desire in the industry to form finFET devices having taller fins. EPI growth on taller fins may be problematic in state of the art processes, as illustrated below and in FIGS. 4 and 5.
In order to achieve smaller fin pitch, while maintaining sufficient fin area size, designers have turned to forming taller fins. Forming taller fins generally calls for setting the recess line for etching fins at a higher level. FIG. 4 illustrates a stylized, cross-sectional view of a typical set of fins of a finFET device having a higher recess line. FIG. 5 illustrates a stylized, cross-sectional view of typical finFET device having EPI formations on its fins having a higher recess line. Referring simultaneously to FIGS. 4 and 5, a finFET device 400 having a higher recess line is illustrated. A plurality of fins 430 are formed on a silicon layer 410. A silicon oxide layer 420 is formed over the silicon layer 410. The fins 430 have a 1st height of “a.”.
In order to maintain taller fin specifications (e.g., fin height “a”), the recess line with respect to an etching process is set at a higher level. FIGS. 4 and 5 show a recess line 440 at the top of the fins 430 after a typical hard mask strip process (e.g., strip of silicon nitride). The objective of the higher recess line that is to form taller fins as compared to the fins illustrated in FIG. 3.
As noted above, EPI formations on the fin portions above the oxide layer 420 are desirable. Using traditional epitaxial growth, which is generally implemented to form an EPI layer over the fin portions rising above the oxide layer 420, the diamond shaped EPI layers 510 become too large. As illustrated in FIG. 5, the EPI layers 510 tend to overlap each other due to the growth of the EPI layer over the span of the fin portions rising above the oxide layer 420.
The overlapping of the EPI formations 510 (merged fins) may cause various problems in the final manufactured IC devices. For example, the overlapping of the EPI formations 510 causes the devices 400 to become irregular. This may result in transistors that operate inconsistently. Transistors or other IC devices manufactured from semiconductor wafers having these overlapping EPI formations 510 may operate inconsistently from devices manufactured from another semiconductor wafer having similar EPI formations 510. Further, the overlapping of the EPI formations 510 may cause the processing of semiconductor wafers to become more uncontrollable, leading to various design violations. This can cause various problems in the manufacturing of IC devices.
Moreover, in memory devices, e.g., SRAMs, the fins 410 may represent N-fins and p-fins, which may be formed consecutively. In this case, the overlapping of the EPI formations 510 would cause shorting of the device 400. Thus, memory devices having the EPI formations 510 of FIG. 5 can cause various shorts, leading to device errors.
Designers have attempted to at least partially alleviate these concerns by forming narrower EPI formations on taller fins, as illustrated by FIGS. 6 and 7. FIG. 6 illustrates a stylized, cross-sectional depiction of a typical finFET device having an EPI growth. FIG. 7 illustrates a stylized, cross-sectional depiction of a typical finFET device having an elliptical EPI growth.
Referring simultaneously to FIGS. 6 and 7, a transistor 600 has a plurality of fins 630. The fins 630 are formed on a silicon layer 610. A silicon oxide layer 620 is formed over the silicon layer 610. As shown in FIGS. 6 and 7, EPI growth/formation may be performed to form EPI formations 640 or 710 on the fins 630. The EPI formations 640 shown in FIG. 6 are formed in a diamond shape starting atop the silicon oxide layer 620. The EPI formations 710 shown in FIG. 7 are formed in an oval shape starting atop the silicon oxide layer 620.
In order to form narrower EPI formations, designers resort to employing different growth rates on different planes of EPI formations. During the epitaxy growth process, etching gas (e.g., HCI gas) may be added to the process gas to selectively grow EPI structures. That is, epitaxial growth of the epitaxy layer 610 may be halted to introduce etching gas. Therefore, epitaxial growth and the etching of a portion of the epitaxy layer 610 may be performed in the same chamber with no intervening vacuum break. This process provides resulting elliptical EPI structures 710 (FIG. 7), which are narrower than the EPI structures of FIG. 6. One such elliptical EPI structure is described in U.S. Patent App. No. 2011/0210404. However, this process calls for more complex manufacturing processes, which increases the cost of manufacturing. Further, this process requires longer EPI deposition time, which also causes manufacturing complexities, delays, and costs.
The present disclosure may address and/or at least reduce one or more of the problems identified above.